This Paper Is Valuable in to Hardware as Well as Software Design Research
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Abstract
The use of on chip networks as interconnection media for systems implemented in FPGAs is express by the amount of logical resource necessary to deploy the network in the target device, and the time necessary to accommodate the network parameters to accomplish the performance goal for the system. In this paper nosotros present a switch architecture, with data catamenia control based on circuit switching and aimed for on-flake networks with a Spidergon topology, which seeks to reduce the area occupied without severely affecting the overall network performance. Equally a consequence, nosotros obtained a switch that requires simply 114 slices in its almost economic version on a Virtex 4-device. We also provide a functioning contour, obtained past subjecting a network formed by these switches to different synthetic workloads inside a simulator. This simulator was adult every bit part of the design flow of the switch, and it proves to be an essential tool for the test and validation process.
Keywords:
NoC
SoC
FPGA
RTL
simulator
hardware software co-pattern
Resumen
El uso de redes en chip como medio de interconexión para sistemas digitales implementados en FPGA se encuentra limitado por la cantidad de recursos lógicos necesarios para implementar la infraestructura de red dentro del dispositivo, además del tiempo necesario para el ajuste de características de la cherry para obtener las metas de desempeño requeridas por el sistema. En este documento presentamos una arquitectura para conmutadores de red en bit, con control de flujo de datos basado en conmutación de circuitos, desarrollada con el objetivo de formar redes de topología Spidergon, y buscando reducir el área necesaria para su implementación sin castigar sobremanera el desempeño de la red. Como resultado de nuestro trabajo presentamos un conmutador que requiere solamente 114 slices de un dispositivo Virtex 4, en su versión más económica. Además proveemos de un perfil de desempeño de una cherry formada por nuestros conmutadores dentro de united nations simulador a medida. Este simulador fue desarrollado como parte del flujo de diseño del conmutador y demostró ser una herramienta esencial para la prueba y la validación del módulo.
Total Text
1 Introduction Network on-Chip (NoC) is an emerging applied science for interconnecting functional blocks in a digital system consisting of multiple processing units. The concept of NoC [1, 7, 8] has attracted involvement in academia and in the development of commercial applications [9]. All the same, even with multiple enquiry teams working on new developments, the NoC interconnect structures have not reached a technical maturity for emerging as the communication infrastructure that gives solution to the challenges present in mod digital systems. A Network-on-Chip is the adaptation of the concept of computer networks practical within an integrated excursion. The network concept from computer science includes the interconnection of computers or network resources that could be mass storage units (NAS or SAN), firewalls, or dedicated servers; all of them sharing information through the network infrastructure, made of routers, switches, or bridges. The operation of a computer network is defined by its topology, the method of controlling data menses and the strategy used to guide the data through the network. To basis these concepts in silicon, it is necessary to tailor the feel in the area of computer networks to a more restricted environment, such as an integrated circuit. In an integrated excursion, the processing elements are represented by IP blocks, full general purpose processors, or retention elements. The interconnection infrastructure tin can be reduced to routers or switches, given the limited surface area in which the digital system may extend, and the transmission medium is equanimous of metallic lines inside the integrated circuit. The network operation is proportional to the amount of information that moves between its members and the time that the communication channels are active. Some previous work in the surface area of on-chip networks that are worth mentioning are the following: PNOC [2], this piece of work was develop for reconfigurable devices. PNOC implements two different kinds of network switches, one for single processing units that can communicate inside a small group of same, known every bit processing island, and another for a message passing between different islands. CUNOC [10] is an on-chip network with a data flow command based on package switching, because CUNOC uses a mesh topology, there must be two flavors of switches: one for the edges of the network and another for the central area. SoCWire [11] is an on-chip network developed with the objective of being uniform with the SpaceWire data transfer protocol [12]. This protocol is currently in employ on missions of the European Space Agency. Star- Wheels [13], this network has a foray into the new "bicycle" topology, which is very similar to Spidergon topology [4] just with the deviation of implementing a "super" network switch in the middle of the communication infrastructure. For a wider survey on on-chip networks, refer to [14]. The architectural design of the network switch was made keeping in mind that the module was aimed to be simple and lightweight. Considering of these objectives, we needed a topology that promoted these characteristics. Nosotros chose Spidergon as the topology to be targeted because it is regular and symmetrical; these two characteristics mean that the network would look the same from whatever signal of the net; and therefore, all the switches would be the aforementioned. In addition, a Spidergon switch does non accept a complete connection between all its communication channels, but rather it only provides links betwixt input/output ports as shown in Figure 1. For case, the right communication channel, from a Spidergon switch, tin can only manage data transfers betwixt it and the left channel and the processing unit channel. A Thorough analysis of the properties of the Spidergon topology fall outside of the scope of this certificate, but a comprehensive treatise can be found in [ten]. Since the selected goal was the optimization of the logical resources needed to deploy 1 switch, a connection-oriented philosophy for controlling information menses between switches was chosen. This philosophy is known as circuit switching, and it reduces the number of storage elements needed to handle the transactions of information between switches. The reduction of storage elements takes identify because, before every data transaction occurs, there must be a concrete connection between the source and the destination. One time the connexion is made, the data will flow as if there were a hard link between the two nodes, and temporary storage for message forwarding will not exist necessary. Broadly speaking, the human relationship between network switches during a data transfer operation occurs every bit follows: Suppose the proposed network is as illustrated in Figure ii. The transaction starts when at that place is a demand to transmit information between the nodes "02" and "07" of the network. A node is defined by a set of one switch and its processing chemical element; even so, all the advice services are provided exclusively by the switch. The path to follow to reach the destination node requires an intermediate hop on node "06", and then that node "02" sends a request for the exclusive use of the output port that connects node "06" to node "07", as Effigy two (a) shows. Node number "06" shall at present evaluate the petition received and determine whether the requested output port is bachelor for assignment or not. In the case of a successful resource allotment by node "06", the request sent from node "02" is transmitted transparently in the direction of the destination node, in this instance node number "07". After this performance, node "06" has already completed its mediation tasks, hence information technology is express to transmit the information received in its input port connected to node "02" to its output port connected to node "07" (This operation does not block the piece of work of arbitration and allocation of the other ports that are not afflicted by communication between nodes "02" and "07"). As opposed to the onetime case, the transaction flow between nodes may not be completed because some resources are non bachelor. Our network switch is designed to handle this kind of situations as testify in Effigy 2 (c, d), where a data link between node "05" and node "07" is desired. In this 2d state of affairs, the way to reach the destination node is by performing a bound through node "06", which is already handling a link between node "02" and node "07"; nevertheless, the cognition of pre-existing connections is non available for each network switch, therefore node "05" sends a request through its output port toward node "07", and this request must make a stop in node "06". Node "06" receives the asking, but it determines that the requested port is currently in utilise, hence it generates a decline bespeak towards node "05". After node "05" gets the pass up signal, it may opt to go on the request and wait for information technology to be resolved satisfactorily, or it can, as in this example, momentarily withdraw its request and make another endeavor after a period of time established by the processing unit. The switch includes four advice channels, each of which is formed by two transmission ports: a port dedicated to information logging, and a port for sending data out of the switch. At the microarchitectural level, each output port is continued to some of the input ports from the other communication channels. The signals on each input port can be classified into control signals and information signals. The control signals are shown in Figure iii; they are used during the germination and destruction of a link between switches. During an functioning of data transmission, the control signals practise not have an active role on the switch. The data signals are used during the establishment of a link as carriers of the address of the destination node; after that, they serve as medium to motility data packages between nodes. The control signals are used at three stages in the switch, these stages are responsible for implementing a policy of "decode - arbitrate - retain". The first stage is implemented by a benefactor module, shown in Figure four, whose primary job is sending all the signals entering the switch through an input port towards the correct output port, which eventually will lead the target node. The mechanism used by the distributor to select which output port is the objective of the request is made from a comparator and a retainer; at this point, the destination address, which is carried by the data signals, is compared with the address of the electric current node. If the addresses are equal, it would mean that the current node is the final destination of the request, therefore, all signals are routed toward the output port of the processing element aqueduct. Otherwise, the asking will go on in the same direction from where it enters the switch, i.e., if entered by the left channel, the point volition abandon the switch through the right aqueduct. As can be noticed, the switch does not take the ability to change the trajectory of the requests, which ways simpler control logic. The propagator module is in charge of passing the results of an mediation process. In other words, it volition let us know if a link has been successfully formed ahead or if the asking has been rejected. The next stage inside the switch is carried out by the allocator. There is an allocator per output port and its task is to cull which request will have exclusive access to the output port. Equally shown in Effigy 5, the allocator is fed by the distributors. The arbiter-servant module asks the priority generator which benefactor will have the highest priority for the electric current arbitration process. The priority generator is a hardware implementation of the round-robin algorithm, meaning that the priority rotates among all entrances to the allocator, always giving lowest priority to the winner of the last resource arbitration procedure. The retention phase affects both the distributor and the allocator that were involved in the terminal successful arbitration process. When the allocator selects a winner, the path betwixt the distributor and the allocator, needs to be locked, so that all information arriving through the input port of the benefactor may go straight to the output port of the allocator. This link must not have whatever meta-states while a release signal (release_in) does not arrive to the allocator. Finally, there is the need to interconnect the distributors with their corresponding allocators; this connection is washed by the transport logic, which consists of an arrangement of customized multiplexors and demultiplexors, designed to interact straight with the control signals from the allocators. Figure vi shows the human relationship betwixt all the modules from the switch. To complete all the stages within a switch, one clock bicycle is needed; for that reason, the default latency between two nodes is equal to the number of hops between them. The inverse process of trigger-happy down a link between two nodes also takes one clock bicycle per switch to be completed; even so, once a switch has received the tear down betoken, it is set to establish a unlike link at the next clock cycle. As part of the evolution menstruum of our switch, nosotros fabricated a network simulator. The principal role of the simulator was to provide a framework where we tin can test unlike combination of values for the switch parameters; for example, we can generate an estimate of performance for a network made of xvi switches, in one case we get the approximate, we tin change the number of data lines between nodes and resimulate the network to know how these changes affect the performance. The simulator was designed under an object- oriented epitome [v, 6]. The data infrastructure was modeled past means of 3 classes; 1 that represents the network switches in a true bit and wheel way, a generator class that is responsible for imitating the operations that a processing chemical element ordinarily would do. The generator class is one of the most important factors in the simulator because it determines when to first a asking for communication, how ofttimes the request is released, to whom the asking is directed, the size of the information packages, how to set the release signal one time a communication is over and treatment the network contentions. This class was modeled by means of a finite state machine shown in Figure 7. Finally, a 'Net' class is used as a container for all the pairs "generator - switch." Besides a container, the internet class gives orders to every chemical element most what needs to be done to carry out the simulation, and to register all events going on in the simulated network. In Figure 8, we provide a class diagram of all the members of the simulator, as well their methods and attributes. This grade describes all the behaviors and internal states from a hardware switch; for instance, control and information signals are represented as boolean attributes. All the attributes are grouped by the input/output port to which they belong, and all the attributes that serve as communication points betwixt instances of the switch course are made public. The Switch course uses viii methods to imitate the behavior of the hardware module, all these methods are shown in figure 8 and are used for tasks such equally setting the initial values for the attributes that will be used in the simulation. A brief description of what happens during a simulation bike within each switch case is equally follows: The update switch method is the interface with the other classes and is in charge of calling all the subsequent methods to complete a simulation wheel. The first task that must exist done is executing the _update_rqs() method, this method works like a positive border of a clock point, when this method is called, all the values from the attributes representing the output ports from the neighbors switches are copied to the attributes representing the input ports of the instance that called the method; all the values obtained in this way are used by the _update_ The generator instances are paired with the switch objects to form a network node in the simulator. This class sends all the stimuli that a processing element would ship to the networks switch. Broadly speaking, the generator can split up its functions in transmission and reception operations, and the transmissions going out the node are managed by the FSM shown in Figure seven. Nevertheless, it is worth noting that the routing decisions are made within the method _routing(). This method selects the traffic pattern that will be used by the node during the entire simulation. Each generator instance can select unlike traffic patterns by sending the right parameters to the _routing() method. In order to add together new patterns to this routine, the user must innovate the lawmaking with the new algorithm to select the valid targets nodes for communications going out of this node. A code snippet of the _routing() method is shown. if traffic == 1: while Truthful: Self.out_port['addr_out'] = random.randrange / (1, self._out_status['total_nodos']+i) if self.out_port['add_out'] != self._addr_my: intermission The reception performance is limited to generate control signals to acknowledge the acceptance of incoming requests. Once a request has arrived to a generator in idle country, the finite state automobile shown in Figure nine, releases the cts indicate to let the source of the request know that it is clear to receive data packages. One time the number of simulation cycles necessary for the finalization of the manual of the information have taken identify, the _fsm_rx() routine, which implements the reception operations, sends a release signal to every switch object in the advice path to let them know that the manual of data is over and the resources assigned must exist deallocated. The timing, for the execution of all actions needed to complete a simulation cycle, is provided by the net class. Kickoff, information technology receives the parameters to configure the simulation. The user provides these parameters by means of a command line interface that contains the number of nodes, number of cycles that the simulation will last, the size of packages, number of information lines between nodes, how often the nodes will release a request and the traffic pattern for each node. In one case the information is in possession of a internet object, it starts to create instances of switch and generator classes. The configuration parameters for each created object are passed past the _deploy_net() method, and these parameters are used past the _init_() routines of each object for their initialization. After the simulated network has been initialized, a cyclic serial of steps are executed starting with the _clock_edge() routine. This routine will trigger an update of the attributes representing the input ports of each switch object. The adjacent step has as its goal the execution of all arbitration processes on each switch object and the evaluation of the finite state machine on every generator instance; this footstep is executed by the _sim_tick() routine. At this point, all the processes regarding the functional units of the network have been executed; hence, the final stride is to annals the internal country of each network switch and generator called. This action is performed past the _observer_log(). This method has admission to all the internal state attributes of the generator and switch instances; thus, it will create log files as the one shown in Figure ten for each network node on the network. All the steps in a higher place are repeated once for each simulation cycle requested past the user. Workloads are one of the nearly important elements in the simulations of on fleck networks. The workload represents the exam information to be released on the simulated network; this data represents requests for data transmissions. A workload planned as well lightly can result in slanted performance profiles, showing merely the best or the worse behavior of the network. For this work, we used synthetic workloads to simulate possible scenarios in a digital system. The flexibility of the use of synthetic loads lies in the possibility of varying the traffic blueprint, the addresses to which each network switch can communicate, and the frequency with which each node releases a communication request to the network. For case, a random workload volition allow each node in the network to be a possible target for a advice, while a restricted workload could just allow communications to nodes numbered "05", "03" and "07". All results presented in this paper used the side by side setup: the switch was implemented in a Virtex four - xc4vlx100-11ff1513, using the synthesis tool provided by the manufacturer. The performance results were obtained using the simulator developed specifically for this network. A detailed look at the logic resources occupied by every unmarried internal component of the switch, every bit shown in Figure 11, lets us know that the critical path of combinational delays is going to be inside the allocators. These results about occupied expanse should not vary in a drastic style, cheers to the decoupling between the control and data signals. For the correct characterization of the switch performance, we synthesized iv different switches with a different number of lines for the data transaction between them. Figure 12 shows the occupation for each switch model. It is worth noting that the increment in the width of de data lines has influence on the occupation considering of the relation between the information signals and the distributors of the switch; each distributor requires united states to compare the address of the destination node and its address. This performance infers a comparator with a width equal to the number of data signals, as they deport the destination accost. The average percent of extra resources needed to increment the number of data lines is around 43.33% between switch models. The most affected resources are the flip-flops from the FPGA, as they are needed in each input and output of the switch to provide a synchronous operation. Information technology is non possible to utilize BRAMs because of the distributed nature of the communications channels of the switch: therefore, they are implemented using the logic element of the FPGA. Every bit a maximum operation frequency we obtained 238.66MHz for the 32 data lines model of the switch. All other models results can be consulted in Effigy 12. Nosotros developed three scenarios with the following characteristics in common: Each network was composed of 16 nodes. Nosotros permit the simulations run for 25,000 clock cycles, and the information transactions consisted of packages of 256 bytes. The results presented in this department are the average from running a single scenario 10 times; this methodology was used to mitigate the presence of all-time/worst case for the simulation. In particular, the offset scenario interconnecting each network node, with data links of 8 bits wide, uses activation periods of between ten% and xc%. The latter refers to the probability that each node would like to get-go a information transaction when it is in idle, and finally the traffic blueprint is random, and so each node can select as a valid target all other nodes of the network. The simulator generates logs with the behavior of each node of the network. The following data are found in these logs: at which clock cycle a node generated a request, the answers to its requests, how much time it spent waiting to restart the request for a link after a reject betoken, the time spent simulating an internal processing in the node, and how many cycles it was inactive. Effigy 13 shows a summary of the log generated for node number 15 in one simulation from scenario 1. In item, this node presented an activation blueprint of ninety%; hence, each time it was able, it requested communication with another node. One of the most important parameters to measure out in network is the latency or boilerplate fourth dimension that would take to complete a satisfactory link betwixt 2 nodes of the network. This parameter is highly volatile as it is affected by the current traffic on the network, for instance, if just a few nodes are transmitting data so there would be a few paths occupied and so in that location would not be the demand to wait for "resource contentions". Every bit latency itself is not a reliable measure, we use a relation betwixt the latency and the number of already established paths around the network. Using this relation we can evaluate the average latency of dissimilar on-flake networks, even if they apply unlike topologies or data-menses controls. In Figure 14, we nowadays the boilerplate latency presented in a single switch and only for 1 simulation run under scenario two, which consists of a network formed by sixteen nodes with 16-bit data links in width, activation patterns between ten% and 90%, and a random traffic design. Equally we can see, when ten of the 16 nodes are trying to plant a connection, the network was capable of handling 9 of the connexion requests satisfactorily. For global results we present the average latency of all nodes of the network from the ten runs of each scenario equally shown in Figure 16 (a). Another cardinal parameter to evaluate a network on-scrap, and therefore their switches, is the average operation, which nosotros can think of every bit the number of connections between nodes that tin concur the network simultaneously, in contrast with the full number of attended and unattended requests that are around the network. For instance, Figure 15 shows the boilerplate performance of one node during x simulations under scenario three, which consists of a network formed by 16 nodes with viii-bit width data links, activation patterns of 100%, and a restricted traffic pattern. The performance results for the simulation of 10 runs of each scenario are presented in Effigy 16 (b). In this paper we present the description of a novel compages for a network switch, involving a circuit switching technique, targeted to networks with a Spidergon topology. As a issue, the necessary logic elements for the deployment of the network infrastructure are reduced to a minimum. In add-on to the light weight architecture, the switch offers warranties once a path betwixt two nodes has formed, as in-order data arrival. It is worth noting from Figure 12 that the best balance between logic resource consumption and operation frequency is delivered past the implementation of the switch with sixteen-chip width information ports. In addition to the latter, this switch model can form NoCs with an platonic bandwidth of ii.29Mb/Seg in their bisection. The smallest switch of the family presents 8 lines for data transactions. This small module can find a place even on small-scale FPGA devices. As an case of this, a network formed by 16 of these switch needs only iii.648% of the Virtex 4 device. To have a better perspective of our small gene switch, Figure 17 shows a contrast between the switches proposed in: CoNoChi[fifteen], CuNoC[10], DyNoC[xvi], PNoC[two], QuarC[17], RMBoC[3] and SoCWire[11]. It is easy to see that our module with 32 data lines has the lowest resource requirements; however, it is worth noting that the switches presented in the other works have added more characteristics to their pattern such equally mistake treatment, quality of service and reliability enhancements. In the absenteeism of a network simulator, the profiling of the switch functioning on an on-flake network, under dissimilar stress levels, would have been a more time-consuming job because of the fourth dimension needed to design hardware modules that would play the office of processing elements, and as a outcome, we would have had to use a limited number of scenarios for the profiling. In regards to the boilerplate latency, shown in Figure 16 (a), nosotros can notice that information technology remains under 300 clock cycles, even with a high number of requests around the network. However, information technology is worth noting that the use of a restricted traffic blueprint, every bit in scenario number three, improves the average latency even more than incrementing the number of data lines connecting each node with its neighbors. If the traffic design is previously known for a system, the correct way to meliorate the latency volition exist to locate IPs with heavy communication necessities near each other; nevertheless, this is not always possible, thus the increase of the number of information lines will be an acceptable choice but with a logical resource penalization. As for the performance, a network formed with the switches presented in this paper can handle satisfactorily up to 5 simultaneous requests; after this number, the requests start to collide into each other. This resource contention is independent from the model of the switch selected for the network. The ineffectiveness of incrementing the number of data lines is shown in Figure 16 (b) on the results between scenario ii and scenario 3. Nonetheless, the analysis of the performance for the scenario 3, which uses a restricted traffic blueprint, shows that the utilise of smart planned traffic patterns tin can improve significantly the functioning of the network. In this particular case the network in scenario 3 was able of handling an average of 11 requests at a maximum workload on the network. An average from the iii scenarios gives u.s. an idea of what we can await from the network nether unknown circumstances; for example, we can see that the maximum operation that it can achieve is 57%, i.due east., treatment ix links simultaneously between network nodes. Even so, if all members of the network make a simultaneous asking, the performance will drop inevitably below 31.25%. All results pb us to conclude that a network, with our switch, volition provide a good solution for communications, inside on-chip digital systems with highly restricted logic elements. We also note that the simulator proved to be a valuable tool for evaluating the touch on that some design options have before synthesis.
Acknowledgements
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References
[1]
R. Ho, K.W. Mai, M.A. Horowitz.
The future of wires.
Proceedings of the IEEE, 89 (2001), pp. 490-504
[2]
C. Hilton, B. Nelson.
PNoC: a flexible circuit- switched NoC for FPGA-based systems.
Computers and Digital Techniques, IEE Proceedings -, 153 (2006), pp. 181-188
[3]
C. Bobda, A. Ahmadinia.
Dynamic interconnection of reconfigurable modules on reconfigurable devices.
Design & Examination of Computers, IEEE, 22 (2005), pp. 443-451
[4]
One thousand. Coppola, M.D. Grammatikakis, R. Locatelli, Yard. Maruccia, L. Pieralisi.
Design of Toll-Efficient Interconnect Processing Units: Spidergon STNoC, CRC Press, Inc, (2008),
[five]
Learning Python: Powerful Object-Oriented Programming, O'Reilly Media, Inc, (2009),
[six]
The Object-Oriented Idea Procedure, Sams, (2000),
[vii]
W.J. Dally, B. Towles.
Road packets, not wires: on-chip interconnection networks.
[8]
G. Mas, P. Martin.
Network-on-chip: the intelligence is in the wire.
Computer Design: VLSI in Computers and Processors, pp. 174-177
[9]
T.G. Mattson, R.F. Van der Wijngaart, Yard. Riepen, T. Lehnig, P. Brett, W. Haas, P. Kennedy, J. Howard, S. Vangal, N. Borkar, Thousand. Ruhl, South. Dighe.
The 48-core SCC Processor: the Programmer's View.
Loftier Performance Computing, Networking, Storage and Analysis (SC), pp. 1-eleven
[10]
S. Jovanovic, C. Tanougast, Due south. Weber, C. Bobda.
CuNoC: A Scalable Dynamic NoC for Dynamically Reconfigurable FPGAs.
Field Programmable Logic and Applications, pp. 753-756
[11]
B. Osterloh, H. Michalik, B. Fiethe, K. Kotarowski.
SoCWire: A Network-on-Chip Approach for Reconfigurable Organisation-on-Scrap Designs in Space Applications.
Adaptive Hardware and Systems, pp. 51-56
[12]
S.1000. Parkes, P. Armbruster.
SpaceWire: a spacecraft onboard network for real-time communications.
[13]
D. Gohringer, L. Bin, K. Hubner, J. Becker.
Star- Wheels Network-on-Chip featuring a self-adaptive mixed topology and a synergy of a circuit - and a package-switching communication protocol.
Field Programmable Logic and Applications, pp. 320-325
[14]
O. Tayan.
Networks-on-Bit: Challenges, trends and mechanisms for enhancements.
Information and Communication Technologies, pp. 57-62
[15]
T. Pionteck, R. Koch, C. Albrecht.
Applying Partial Reconfiguration to Networks-On-Chips.
Field Programmable Logic and Applications, pp. 1-6
[16]
C. Bobda, A. Ahmadinia, M. Majer, J. Teich, Due south. Fekete, J. van der Veen.
DyNoC: A dynamic infrastructure for communication in dynamically reconfugurable devices.
Field Programmable Logic and Applications, pp. 153-158
[17]
M. Moadeli, W. Vanderbauwhede, A. Shahrabi.
Quarc: A Novel Network-On-Chip Architecture.
Parallel and Distributed Systems, pp. 705-712
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